CY7C185
Switching Waveforms
Read Cycle No.1
[10,11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No.2
[12,13]
CE
1
t
RC
CE
2
OE
OE
t
ACE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
ICC
50%
ISB
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[11,13]
t
WC
ADDRESS
CE
1
t
AW
CE
2
CE
WE
t
SA
t
SCE2
t
PWE
t
SCEI
t
HA
OE
t
SD
DATA I/O
NOTE 14
t
HZOE
10.
11.
12.
13.
Device is continuously selected. OE, CE
1
= V
IL
. CE
2
= V
IH
.
WE is HIGH for read cycle.
Data I/O is High Z if OE = V
IH
, CE
1
= V
IH
, WE = V
IL
, or CE
2
=V
IL
.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH and WE LOW. CE
1
and WE must be LOW and CE
2
must be HIGH
to initiate write. A write can be terminated by CE
1
or WE going HIGH or CE
2
going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
t
HD
DATA
IN
VALID
Document #: 38-05043 Rev. *A
Page 5 of 11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
