CY7C168A
4Kx4 RAM
Features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— t
AA
= 15 ns
• Low active power
— 633 mW
• Low standby power
— 110 mW
• TTL-compatible inputs and outputs
• V
IH
of 2.2V
• Capable of withstanding greater than 2001V electrostat-
ic discharge
Functional Description
The CY7C168A is a high-performance CMOS static RAM or-
ganized as 4096 by 4 bits. Easy memory expansion is provided
by an active LOW Chip Enable (CE) and three-state drivers.
The CY7C168A has an automatic power-down feature, reduc-
ing the power consumption by 77% when deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
four data input/output pins (I/O
0
through I/O
3
) is written into the
memory location specified on the address pins (A
0
through
A
11
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the location specified on the
address pins will appear on the four data input/output pins
(I/O
0
through I/O
3
).
The input/output pins remain in a high-impedance state when
Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
CE
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
7C168A 16
\
15
14
13
12
11
INPUTBUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
ROW DECODER
I/O
0
SENSE AMP
128 x 128
ARRAY
I/O
1
I/O
2
I/O
3
V
CC
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
WE
C168A-2
COLUMN
DECODER
POWER
DOWN
(7C168A)
CE
WE
A
7
A
8
A
9
A
10
A
11
C168A-1
Selection Guide
7C168A-15
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Military
15
115
-
7C168A-20
20
90
100
7C168A-25
25
90
100
7C168A-35
35
90
100
7C168A-45
45
90
100
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 3, 2000