欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY7C146-55JC 参数 Datasheet PDF下载

CY7C146-55JC图片预览
型号: CY7C146-55JC
PDF下载: 下载PDF文件 查看货源
内容描述: 2Kx8双口静态RAM [2Kx8 Dual-Port Static RAM]
分类和应用:
文件页数/大小: 18 页 / 341 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
 浏览型号CY7C146-55JC的Datasheet PDF文件第1页浏览型号CY7C146-55JC的Datasheet PDF文件第2页浏览型号CY7C146-55JC的Datasheet PDF文件第3页浏览型号CY7C146-55JC的Datasheet PDF文件第5页浏览型号CY7C146-55JC的Datasheet PDF文件第6页浏览型号CY7C146-55JC的Datasheet PDF文件第7页浏览型号CY7C146-55JC的Datasheet PDF文件第8页浏览型号CY7C146-55JC的Datasheet PDF文件第9页  
CY7C132/CY7C136
CY7C142/CY7C146
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
R2
347Ω
R1893Ω
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R2
347Ω
C132-5
R1893Ω
5V
281Ω
BUSY
OR
INT
30pF
(a)
(b)
C132-6
BUSYOutput Load
(CY7C132/CY7C136 ONLY)
ALL INPUT PULSES
Equivalent to:
THVÉNIN EQUIVALENT
3.0V
250Ω
1.4V
10%
90%
OUTPUT
GND
90%
10%
< 5 ns
< 5 ns
]
Switching Characteristics
Over the Operating Range
[6, 11]
7C136-15
[3,4]
7C146-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
[12]
Data Hold from Address Change
CE LOW to Data Valid
[12]
OE LOW to Data Valid
[12]
OE LOW to Low Z
[10, 13]
OE HIGH to High Z
[10, 13, 14]
CE LOW to Low Z
[10, 13]
CE HIGH to High Z
[10, 13, 14]
CE LOW to Power-Up
[10]
CE HIGH to Power-Down
[10]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
[10]
R/W HIGH to Low Z
[10]
0
15
12
12
2
0
12
10
0
10
0
0
15
25
20
20
2
0
15
15
0
15
0
3
10
0
25
30
25
25
2
0
25
15
0
15
3
10
5
15
0
25
0
15
10
3
15
5
15
15
15
0
25
15
3
15
25
25
0
30
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C132-25
[3]
7C136-25
7C142-25
7C146-25
Min.
Max.
7C132-30
7C136-30
7C142-30
7C146-30
Min.
Max.
Unit
WRITE CYCLE
[15]
4