CY7C1354B
CY7C1356B
Logic Block Diagram-CY7C1356B (512K x 18)
A0, A1, A
MODE
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP
a
DQP
b
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
CY7C1354B-225
CY7C1356B-225
2.8
250
35
CY7C1354B-200
CY7C1356B-200
3.2
220
35
CY7C1354B-166
CY7C1356B-166
3.5
180
35
Unit
ns
mA
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05114 Rev. *C
Page 2 of 29
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