CY7C1354B
CY7C1356B
Partial Write Cycle Description
[1, 2, 3, 8]
Function (CY7C1354B)
Read
Write –No bytes written
Write Byte a– (DQ
a
and DQP
a)
Write Byte b – (DQ
b
and DQP
b)
Write Bytes b, a
Write Byte c – (DQ
c
and DQP
c)
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
d
and DQP
d)
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BW
d
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
BW
c
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
BW
b
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
BW
a
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW
[a:d]
is valid. Appropriate write will be done based on which byte write is active.
Function (CY7C1356B)
Read
Write – No Bytes Written
Write Byte a
−
(DQ
a
and DQP
a)
Write Byte b – (DQ
b
and DQP
b)
Write Both Bytes
WE
H
L
L
L
L
BW
b
x
H
H
L
L
BW
a
x
H
L
H
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354B/CY7C1354B incorporates a serial boundary
scan Test Access Port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This port
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
SS
) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to V
DD
through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Page 10 of 29
Document #: 38-05114 Rev. *C
CYPRESS [ CYPRESS SEMICONDUCTOR ]
