CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms
(continued)
Write Cycle No. 1 (OE Three-States Data I/Os—Either Port
Either Port
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
OE
t
HZOE
D
OUT
HIGH IMPEDANCE
DATA VALID
t
HD
t
AW
t
PWE
t
HA
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
t
HZWE
DATA
OUT
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t
SD
.
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
t
HA
t
AW
t
PWE
t
HD
DATA VALID
t
LZWE
HIGH IMPEDANCE
Document #: 38-06002 Rev. *D
Page 9 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
