CY7C1041B
Switching Characteristics
[4]
Over the Operating Range
7C1041B-12
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
V
CC
(typical) to the First Access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
Byte Enable to End of Write
10
12
10
10
0
0
10
7
0
3
6
12
0
6
15
12
12
0
0
12
8
0
3
7
12
0
12
6
0
7
17
14
14
0
0
14
8
0
3
7
3
6
0
15
7
0
7
0
6
3
7
0
17
7
3
12
6
0
7
3
7
1
12
12
3
15
7
0
7
1
15
15
3
17
7
1
17
17
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1041B-15
Min.
Max.
7C1041B-17
Min.
Max.
Unit
Write Cycle
[8, 9]
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
power
time has to be provided initially before a read/write operation is
started.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05142 Rev. *A
Page 4 of 11
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