CY7C1021DV33
1-Mbit (64K x 16) Static RAM
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Pin-and function-compatible with CY7C1021CV33
• High speed
— t
AA
= 10 ns
• Low active power
— I
CC
= 60 mA @ 10 ns
• Low CMOS standby power
•
•
•
•
•
— I
SB2
= 3 mA
2.0V data retention
Automatic power-down when deselected
CMOS for optimum speed/power
Independent control of upper and lower bits
Available in Pb-free 44-pin 400-Mil wide Molded SOJ,
44-pin TSOP II and 48-ball VFBGA packages
Functional Description
[1]
The CY7C1021DV33 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA
packages.
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document #: 38-05460 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 8, 2006
CYPRESS [ CYPRESS SEMICONDUCTOR ]
