CY7C1021BV33
Switching Characteristics
[4]
Over the Operating Range
7C1021BV-8
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
CYCLE
[7]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte Enable to End of Write
8
8
7
6
0
0
6
4
0
3
4
8
10
8
7
0
0
8
6
0
3
5
8
12
9
8
0
0
8
6
0
3
6
9
15
10
10
0
0
10
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
0
4
0
5
0
12
3
4
0
12
5
0
6
0
4
3
5
0
12
6
0
7
3
8
4
0
5
3
6
0
15
7
8
8
3
10
4
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1021BV-10
Min.
Max.
7C1021BV-12
Min.
Max.
7C1021BV-15
Min.
Max.
Unit
Shaded areas contain advance information.
Data Retention Characteristics
Over the Operating Range (L version only)
Parameter
V
DR
I
CCDR
t
CDR[9]
t
R[10]
Description
V
CC
for Data Retention
Data Retention Current
Com’l
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
0
t
RC
Conditions
[8]
Min.
2.0
100
Max.
Unit
V
µA
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. No input may exceed V
CC
+ 0.5V.
9. Tested initially and after any design or process changes that may affect these parameters.
10. t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 and slower speeds.
Document #: 38-05148 Rev. *A
Page 4 of 11
CYPRESS [ CYPRESS SEMICONDUCTOR ]
