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CY7C1019CV33-12VC 参数 Datasheet PDF下载

CY7C1019CV33-12VC图片预览
型号: CY7C1019CV33-12VC
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8静态RAM [128K x 8 Static RAM]
分类和应用:
文件页数/大小: 8 页 / 196 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1019CV33
128K x 8 Static RAM
Features
• Pin and function compatible with CY7C1019BV33
• High speed
— t
AA
= 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 32-pin TSOP II and 400-mil SOJ package
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.
Functional Description
The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Logic Block Diagram
Pin Configuration
SOJ/TSOP II
Top View
A
0
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
I/O
INPUT BUFFER
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
ROW DECODER
1
I/O
SENSE AMPS
2
512 x 256 x 8
ARRAY
I/O
I/O
I/O
I/O
I/O
3
4
5
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
6
7
Selection Guide
7C1019CV33-8
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
8
85
5
7C1019CV33-10
10
80
5
7C1019CV33-12
12
75
5
7C1019CV33-15
15
70
5
Unit
ns
mA
mA
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Cypress Semiconductor Corporation
Document #: 38-05130 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised December 16, 2002