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CY7B991-5JC 参数 Datasheet PDF下载

CY7B991-5JC图片预览
型号: CY7B991-5JC
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程偏移时钟缓冲器 [Programmable Skew Clock Buffer]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 15 页 / 290 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7B991
CY7B992
Electrical Characteristics
Over the Operating Range
[6]
CY7B991
Parameter
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three-Level Input HIGH
Voltage (Test, FS, xFn)
[7]
Three-Level Input MID
Voltage (Test, FS, xFn)
[7]
Three-Level Input LOW
Voltage (Test, FS, xFn)
[7]
Input HIGH Leakage Current
(REF and FB inputs only)
Input LOW Leakage Current
(REF and FB inputs only)
Input HIGH Current
(Test, FS, xFn)
Input MID Current
(Test, FS, xFn)
Input LOW Current
(Test, FS, xFn)
Output Short Circuit
Current
[8]
Operating Current Used by
Internal Circuitry
Output Buffer Current per
Output Pair
[9]
Power Dissipation per
Output Pair
[10]
Min.
V
CC
Max.
Min.
V
CC
Max.
Min.
V
CC
Max.
V
CC
= Max., V
IN
= Max.
V
CC
= Max., V
IN
= 0.4V
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
V
CC
= Max., V
OUT
= GND (25
°
C only)
V
CCN
= V
CCQ
=
Max., All Input
Selects Open
Com’l
Mil/Ind
–50
–500
200
50
–200
–250
85
90
14
–50
Test Conditions
V
CC
= Min., I
OH
= –16 mA
V
CC
= Min., I
OH
=–40 mA
V
CC
= Min., I
OL
= 46 mA
V
CC
= Min., I
OL
= 46 mA
2.0
–0.5
V
CC
– 0.85
V
CC
/2 –
500 mV
0.0
V
CC
0.8
V
CC
V
CC
/2 +
500 mV
0.85
10
–500
200
50
–200
N/A
85
90
19
mA
V
CC
1.35
–0.5
V
CC
– 0.85
V
CC
/2 –
500 mV
0.0
0.45
0.45
V
CC
1.35
V
CC
V
CC
/2 +
500 mV
0.85
10
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
Min.
2.4
V
CC
–0.75
V
Max.
CY7B992
Min.
Max.
Unit
V
I
CCN
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0 mA
Input Selects Open, f
MAX
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0 mA
Input Selects Open, f
MAX
PD
78
104
[11]
mW
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal termination resistors hold
unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
LOCK
time
before all datasheet limits are achieved.
8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs
should not be shorted to GND. Doing so may cause permanent damage.
9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
CY7B991: I
CCN
= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B992: I
CCN
= [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F
<
C
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to
the load circuit:
CY7B991: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B992: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1
See note 9 for variable definition.
11. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.
Document #: 38-07138 Rev. **
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