CY7B923
CY7B933
ASYNCHRONOUS FIFO
CLOCKED FIFO
7C42X/3X/6X/7X
FROM CONTROLLER
R
Q
0–8
9
ENR
CKR
7C44X/5X
Q
0–8
9
ENA
CKW
RP
7B923
D
0–7
, SC/D
ENN
CKW
7B923
D
0–7
, SC/D
HOTLink TRANSMITTER
HOTLink TRANSMITTER
HOTLink RECEIVER
7B933
CKR
RDY
Q
0–7
, SC/D
CKR
HOTLink RECEIVER
7B933
RDY
Q
0–7
, SC/D
9
9
W
7C42X/3X/6X/7X
D
0–8
CKW
ENW
7C44X/5X
CLOCKED FIFO
D
0–8
ASYNCHRONOUS FIFO
Figure 4. Seamless FIFO Interface
Bypass Mode Operation
In Bypass mode the input data is interpreted as ten (10) bits
(D
b–h
), SC/D (D
a
), and SVS (D
j
) of pre-encoded transmission
data to be serialized and sent over the link. This data can use
any encoding method suitable to the designer. The only
restrictions upon the data encoding method is that it contain
suitable transition density for the Receiver PLL data synchro-
nizer (one per 10 bit byte), and that it be compatible with the
transmission media.
Data loaded into the Input register on the rising edge of CKW
will be loaded into the Shifter on the subsequent rising edges
of CKW. It will then be shifted to the outputs one bit at a time
using the internal clock generated by the clock generator. The
first bit of the transmission character (D
a
) will appear at the
output (OUTA±, OUTB±, and OUTC±) after the next CKW
edge.
While in either the Encoded mode or Bypass mode, if a CKW
edge arrives when the inputs are not enabled (ENA and ENN
both HIGH), the Encoder will insert a pad character K28.5
(e.g., C5.0) to maintain proper link synchronization (in Bypass
Document #: 38-02017 Rev. *E
mode the proper sense of running disparity cannot be
guaranteed for the first pad character, but is correct for all pad
characters that follow). This automatic insertion of pad
characters can be inhibited by insuring that the Transmitter is
always enabled (i.e., ENA or ENN is hard-wired LOW).
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same infor-
mation and are intended for use in systems with multiple
connections. Each output pair may be connected to a different
serial media, each of which may be a different length, link type,
or interface technology. For systems that do not require all
three output pairs, the unused pairs should be wired to V
CC
to
minimize the power dissipated by the output circuit, and to
minimize unwanted noise generation. An internal voltage
comparator detects when an output differential pair is wired to
V
CC
, causing the current source for that pair to be disabled.
This results in a power savings of around 5 mA for each
unused pair.
In systems that require the outputs to be shut off during some
periods when link transmission is prohibited (e.g., for laser
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CYPRESS [ CYPRESS SEMICONDUCTOR ]
