CY62256V
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[12, 13]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No. 2 (OE Controlled)
[13, 14]
t
RC
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
V
CC
SUPPLY
CURRENT
50%
t
PD
ICC
50%
ISB
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
t
WC
ADDRESS
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 17
t
HZOE
DATA
IN
VALID
t
HD
Notes:
12. Device is continuously selected. OE, CE = V
IL
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
IH
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05057 Rev. *F
Page 6 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
