CY62128V Family
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
62128V–8
Read Cycle No. 2 (OE Controlled)
[11, 12]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
62128V-9
HIGH
IMPEDANCE
I
CC
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[13,14]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
62128V-10
t
HA
t
HD
Notes:
10. Device is continuously selected. OE, CE = V
IL,
CE
2
=V
IH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
13. Data I/O is high impedance if OE = V
IH
.
14. If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
6
CYPRESS [ CYPRESS SEMICONDUCTOR ]
