CY28346-2
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (three-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
Table 6. Cypress Clock Power Management Truth Table
B0b6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B1b6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PD#
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
CPU_STP#
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Stoppable
CPUT
Running
Iref x6
Iref x2
Iref x2
Running
Hi Z
Hi Z
Hi Z
Running
Iref x6
Hi Z
Hi Z
Running
Hi Z
Hi Z
Hi Z
Stoppable
CPUC
Running
Iref x6
Low
Low
Running
Hi Z
Hi Z
Hi Z
Running
Iref x6
Hi Z
Hi Z
Running
Hi Z
Hi Z
Hi Z
Non-Stop CPUT Non-Stop CPUC
Running
Running
Iref x2
Iref x2
Running
Running
Hi Z
Hi Z
Running
Running
Hi Z
Hi Z
Running
Running
Hi Z
Hi Z
Running
Running
Low
Low
Running
Running
Hi Z
Hi Z
Running
Running
Hi Z
Hi Z
Running
Running
Hi Z
Hi Z
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
setup
). (See
Figure 2.)
The PCIF (0:2) clocks will not be affected by this pin
if their control bits in the SMBus register are set to allow them
to be free running.
t
setup
P C I_S T P #
P C IF 33M
P C I 33M
Figure 6. PCI_STP# Assertion Waveforms
Note that the PCI STOP function is controlled by two inputs.
One is the device PCI_STP# pin number 34 and the other is
The deassertion of the PCI_STP# signal will cause all PCI and
SMBus byte 0 bit 3. These two inputs to the function are
stoppable PCIF clocks to resume running in a synchronous
logically ANDed. If either the external pin or the internal
manner within two PCI clock periods after PCI_STP# transi-
SMBus register bit is set low then the stoppable PCI clocks will
tions to a high level.
be stopped in a logic low state. Reading SMBus Byte 0 Bit 3
will return a 0 value if either of these control bits are set LOW
thereby indicating the devices stoppable PCI clocks are not
running.
PCI_STP# Deassertion
Document #: 38-07509 Rev. *A
Page 10 of 20
CYPRESS [ CYPRESS SEMICONDUCTOR ]
