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CY2305SXI-1H 参数 Datasheet PDF下载

CY2305SXI-1H图片预览
型号: CY2305SXI-1H
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3V零延迟缓冲器 [Low-Cost 3.3V Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管
文件页数/大小: 14 页 / 210 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY2305
CY2309
Switching Characteristics for
CY2305SI-1and CY2309SI-1 Industrial Temperature Devices
[7]
Parameter
t1
Name
Output Frequency
Duty Cycle
[6]
= t
2
÷
t
1
t3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Rise Time
[6]
Fall Time
[6]
Output to Output Skew
[6]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[6]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[6]
Device to Device Skew
[6]
Cycle to Cycle Jitter
[6]
PLL Lock Time
[6]
Test Conditions
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2. Measured in
PLL Bypass Mode, CY2309 device
only.
Measured at V
DD
/2 on the CLKOUT
pins of devices
Measured at 66.67 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
Min.
10
10
40.0
1
Typ.
50.0
85
5
Max.
100
133.33
60.0
2.50
2.50
250
±350
8.7
Unit
MHz
MHz
%
ns
ns
ps
ps
ns
70
700
200
1.0
ps
ps
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
[7]
Parameter
t
1
Name
Output Frequency
Duty Cycle
[6]
= t
2
÷
t
1
Duty Cycle
[6]
= t
2
÷
t
1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
8
t
J
t
LOCK
Rise Time
[6]
Fall Time
[6]
Output to Output
Skew
[6]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[6]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[6]
Device to Device Skew
[6]
Output Slew Rate
[6]
Cycle to Cycle Jitter
[6]
PLL Lock Time
[6]
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured at 1.4V, F
out
< 50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2. Measured in
PLL Bypass Mode, CY2309 device
only.
Measured at V
DD
/2 on the CLKOUT
pins of devices
Measured between 0.8V and 2.0V
using Test Circuit #2
Measured at 66.67 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
Description
Min.
10
10
40.0
45.0
1
Typ.
50.0
50.0
85
5
Max.
100
133.33
60.0
55.0
1.50
1.50
250
±350
8.7
Unit
MHz
MHz
%
%
ns
ns
ps
ps
ns
1
60
700
200
1.0
ps
V/ns
ps
ms
Document #: 38-07140 Rev. *G
Page 6 of 14