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CY2305SXC-1HT 参数 Datasheet PDF下载

CY2305SXC-1HT图片预览
型号: CY2305SXC-1HT
PDF下载: 下载PDF文件 查看货源
内容描述: 低成本3.3V零延迟缓冲器 [Low-Cost 3.3V Zero Delay Buffer]
分类和应用: 时钟驱动器逻辑集成电路光电二极管PC
文件页数/大小: 14 页 / 210 K
品牌: CYPRESS [ CYPRESS ]
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CY2305  
CY2309  
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices [7]  
Parameter  
Name  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10  
100  
MHz  
10-pF load  
10  
133.33  
60.0  
2.50  
2.50  
250  
MHz  
%
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
All outputs equally loaded  
40.0  
50.0  
85  
t3  
t4  
t5  
ns  
ns  
ps  
ps  
Fall Time[6]  
Output to Output Skew[6]  
t6A  
Delay, REF Rising Edge to Measured at VDD/2  
±350  
CLKOUT Rising Edge[6]  
t6B  
Delay, REF Rising Edge to Measured at VDD/2. Measured in  
1
5
8.7  
ns  
CLKOUT Rising Edge[6]  
Device to Device Skew[6]  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
PLL Bypass Mode, CY2309 device  
only.  
t7  
Measured at VDD/2 on the CLKOUT  
70  
700  
200  
1.0  
ps  
ps  
pins of devices  
tJ  
Measured at 66.67 MHz, loaded  
outputs  
tLOCK  
Stable power supply, valid clock  
ms  
presented on REF pin  
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices[7]  
Parameter  
Name  
Description  
Min.  
Typ.  
Max.  
Unit  
t1  
Output Frequency  
30-pF load  
10-pF load  
10  
100  
MHz  
10  
133.33  
MHz  
Duty Cycle[6] = t2 ÷ t1  
Duty Cycle[6] = t2 ÷ t1  
Rise Time[6]  
Measured at 1.4V, Fout = 66.67 MHz  
Measured at 1.4V, Fout < 50.0 MHz  
Measured between 0.8V and 2.0V  
Measured between 0.8V and 2.0V  
All outputs equally loaded  
40.0  
45.0  
50.0  
50.0  
85  
60.0  
55.0  
1.50  
1.50  
250  
%
%
ns  
ns  
ps  
ps  
t3  
t4  
t5  
t6A  
Fall Time[6]  
Output to Output Skew[6]  
Delay, REF Rising Edge to Measured at VDD/2  
±350  
CLKOUT Rising Edge[6]  
t6B  
Delay, REF Rising Edge to Measured at VDD/2. Measured in  
1
5
8.7  
ns  
CLKOUT Rising Edge[6]  
Device to Device Skew[6]  
Output Slew Rate[6]  
Cycle to Cycle Jitter[6]  
PLL Lock Time[6]  
PLL Bypass Mode, CY2309 device  
only.  
t7  
Measured at VDD/2 on the CLKOUT  
1
700  
ps  
V/ns  
ps  
pins of devices  
t8  
Measured between 0.8V and 2.0V  
using Test Circuit #2  
tJ  
Measured at 66.67 MHz, loaded  
60  
200  
1.0  
outputs  
tLOCK  
Stable power supply, valid clock  
presented on REF pin  
ms  
Document #: 38-07140 Rev. *G  
Page 6 of 14  
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