CY2305
CY2309
Absolute Maximum Conditions
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF......................................... –0.5V to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature ................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min.
3.0
0
–
–
–
0.05
Max.
3.6
70
30
10
7
50
Unit
V
°C
pF
pF
pF
ms
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Input LOW Voltage
[5]
Input HIGH Voltage
[5]
Input LOW Current
Input HIGH Current
Output LOW
Voltage
[6]
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA (–1)
I
OH =
12 mA (–1H)
I
OH
= –8 mA (–1)
I
OL
= –12 mA (–1H)
REF = 0 MHz
Unloaded outputs at 66.67 MHz,
SEL inputs at V
DD
Test Conditions
Min.
–
2.0
–
–
–
2.4
–
–
Max.
0.8
–
50.0
100.0
0.4
–
12.0
32.0
Unit
V
V
µA
µA
V
V
µA
mA
Output HIGH Voltage
[6]
Power Down Supply Current
Supply Current
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices
[7]
Parameter
t1
Name
Output Frequency
Duty Cycle
[6]
= t
2
÷
t
1
t3
t
4
t
5
t
6A
t
6B
t
7
t
J
t
LOCK
Rise
Fall
Time
[6]
Time
[6]
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Test Conditions
Min.
10
10
40.0
–
–
–
–
1
–
–
–
Typ.
–
50.0
–
–
85
0
5
–
70
–
Max.
100
133.33
60.0
2.50
2.50
250
±350
8.7
700
200
1.0
Unit
MHz
MHz
%
ns
ns
ps
ps
ns
ps
ps
ms
Output to Output Skew
[6]
Delay, REF Rising Edge to Measured at V
DD
/2
CLKOUT Rising Edge
[6]
Delay, REF Rising Edge to Measured at V
DD
/2. Measured in PLL
CLKOUT Rising Edge
[6]
Bypass Mode, CY2309 device only.
Device to Device Skew
[6]
Cycle to Cycle Jitter
[6]
PLL Lock Time
[6]
Measured at V
DD
/2 on the CLKOUT pins
of devices
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
Notes:
5. REF input has a threshold voltage of V
DD
/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
Document #: 38-07140 Rev. *G
Page 4 of 14
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