5
CY2291
Three-PLL General Purpose
EPROM Programmable Clock Generator
Features
Three integrated phase-locked loops
EPROM programmability
Benefits
Generates up to 3 custom frequencies from external sources
Easy customization and fast turnaround
Factory-programmable (CY2291) or field-programmable
Programming support available for all opportunities
(CY2291F) device options
Low-skew, low-jitter, high-accuracy outputs
Power-management options (Shutdown, OE, Suspend)
Frequency select option
Smooth slewing on CPUCLK
Configurable 3.3V or 5V operation
20-pin SOIC Package
Meets critical industry standard timing requirements
Supports low-power applications
8 user-selectable frequencies on CPU PLL
Allows downstream PLLs to stay locked on CPUCLK output
Enables application compatibility
Industry-standard packaging saves on board space
Selector Guide
Part Number
CY2291
CY2291I
CY2291F
CY2291FI
Outputs
8
8
8
8
Input Frequency Range
Output Frequency Range
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–80 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–80 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–60.0 MHz (3.3V)
32XIN
32XOUT
XTALIN
OSC.
XTALOUT
S0
S1
S2/SUSPEND
UPLL
(10 BIT)
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
/2,3,4
CLKA
CLKB
CPLL
(8 BIT)
/1,2,4
XBUF
CPUCLK
Logic Block Diagram
OSC.
32K
MUX
CLKC
CLKD
SPLL
(8 BIT)
CLKF
CONFIG
EPROM
SHUTDOWN/
OE
Cypress Semiconductor Corporation
Document #: 38-07189 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002