CY2280
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
Notes:
4. Electrical parameters are guaranteed with these operating conditions.
5. Crystal Inputs have CMOS thresholds.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Switching Characteristics
[6, 7]
Parameter
t
1
t
2
Output
All
CPUCLK,
APIC
PCICLK
USBCLK,
REF
CPUCLK
CPUCLK
CPUCLK
CPUCLK,
PCICLK
PCICLK,
PCICLK
CPUCLK,
APIC
APIC
CPUCLK
PCICLK
CPUCLK,
PCICLK
Description
Output Duty Cycle
[8]
CPU and APIC Clock
Rising and Falling Edge
Rate
PCI Clock Rising and
Falling Edge Rate
USB, REF Rising and
Falling Edge Rate
CPU Clock Rise Time
CPU Clock Fall Time
CPU-CPU Clock Skew
CPU-PCI Clock Skew
[9]
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V
-1,-11S,
-21S
-1,-11S,
-21S
Test Conditions
Min.
45
1.0
Typ.
50
Max.
55
4.0
Unit
%
V/ns
t
2
t
2
t
3
t
4
t
5
t
6
Between 0.4V and 2.4V
Between 0.4V and 2.4V
Between 0.4V and 2.0V
Between 2.0V and 0.4V
Measured at 1.25V
Measured at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks
Measured at 1.5V
Measured at 1.25V for 2.5V
clocks
Measured at 1.25V
Measured at 1.25V
Measured at 1.5V
CPU, PCI clock stabilization from
power-up
1.0
0.5
4.0
2.0
1.6
1.6
100
175
4.0
V/ns
V/ns
ns
ns
ps
ns
-1,-11S,
-21S
-1,-11S,
-21S
-1,-11S,
-21S
0.4
0.4
1.5
t
7
t
8
t
9
t
10
t
11
t
12
PCI-PCI Clock Skew
CPU-APIC Clock
Skew
[10]
APIC-APIC Clock Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Power-up Time
250
-21S
2.0
100
-1,-11S,
-21S
200
250
4.5
175
250
500
3
ps
ns
ps
ps
ps
ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when V
DD
= 3.3V. When V
DD
= 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S and -21S options.
10. APIC lags CPU for -21S option.
Document #: 38-07207 Rev. *A
Page 5 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
