CY2254A
Pin Summary
Name
−1
−2
Description
VDD
1
1
Voltage supply
XTALIN[1]
XTALOUT[1]
VSS
2
2
Reference crystal input
Reference crystal feedback
Ground
3
3
4
4
OE
5
5
Output Enable, Active HIGH (internal pull-up resistor to VDD
CPU clock output
)
CPUCLK0
CPUCLK1
VDD
6
6
7
7
CPU clock output
8
8
Voltage supply
CPUCLK2
CPUCLK3
VSS
9
9
CPU clock output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU clock output
Ground
S1
CPU clock select input, bit 1 (internal pull-up resistor to VDD
CPU clock select input, bit 0 (internal pull-up resistor to VDD
Voltage supply
)
)
S0
VDD
PCICLK0
PCICLK1
VSS
PCI clock output
PCI clock output
Ground
PCICLK5
PCICLK4
VDD
PCI clock output
PCI clock output
Voltage supply
PCICLK3
PCICLK2
VSS
PCI clock output
PCI clock output
Ground
IOCLK
KBDCLK
USBCLK
VDD
I/O clock output (24 MHz)
Keyboard controller clock output (12 MHz)
Universal Serial Bus clock output (48 MHz)
Voltage supply
25
26
27
28
26
27
28
REF1
Reference clock output (14.318 MHz)
Reference clock output (14.318 MHz)
REF0
Function Table
Ref. Clock
Output
KBDCLK
−1 only
USBCLK
Option
−1,−2
−1,−2
−1,−2
−1,−2
−1
OE S0 S1
XTALIN
CPUCLK
PCICLK
High-Z
IOCLK
High-Z
−2 only
0
1
1
1
1
1
X
0
0
1
1
1
X
0
1
0
1
1
14.318 MHz High-Z
14.318 MHz 50.0 MHz
14.318 MHz 60.0 MHz
High-Z
High-Z
High-Z
25.0 MHz
30.0 MHz
14.318 MHz 24 MHz
14.318 MHz 24 MHz
12 MHz
12 MHz
12 MHz
TCLK/8
48 MHz
48 MHz
48 MHz
14.318 MHz 66.66 MHz 33.33 MHz 14.318 MHz 24 MHz
TCLK[2]
TCLK/2
TCLK/4
TCLK
TCLK/4
−2
14.318 MHz 55.0 MHz
27.5 MHz
14.318 MHz 24 MHz
48 MHz
Notes:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 17 pF.
2. TCLK is a test clock on XTALIN (pin 2) during test mode.
Document #: 38-07203 Rev. *A
Page 2 of 8
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