CY22381
Switching Characteristics
Parameter
1/t
1
t
2
Name
Output Frequency
Output Duty Cycle
Description
Clock output limit, Commercial
Clock output limit, Industrial
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout < 100 MHz, divider >= 2, measured
at V
DD
/2
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout > 100 MHz or divider = 1, measured
at V
DD
/2
t
3
t
4
t
5
t
6
t
7
Rising Edge Slew Rate
Falling Edge Slew Rate
Output Three-state Timing
Clock Jitter
Lock Time
Output clock rise time, 20% to 80% of V
DD
Output clock fall time, 20% to 80% of V
DD
Time for output to enter or leave
three-state mode after SHUTDOWN/OE
switches
Peak-to-peak period jitter, CLK outputs
measured at V
DD
/2
PLL Lock Time from Power up
Min
–
–
45%
Typ.
–
–
50%
Max
200
166
55%
Unit
MHz
MHz
40%
50%
60%
0.75
0.75
–
1.4
1.4
150
–
–
300
V/ns
V/ns
ns
–
–
200
1.0
–
3
ps
ms
Switching Waveforms
Figure 2. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 3. Output Three-State Timing
OE
t
5
ALL
THREE-STATE
OUTPUTS
t
5
Figure 4. CLK Output Jitter
t
6
CLK
OUTPUT
Notes
4. Guaranteed to meet 20% – 80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07012 Rev. *E
Page 5 of 9
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