CY22392
Electrical Characteristics
Parameter
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
LOAD_IN
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
Description
Output High Current
[3]
Output Low Current
[3]
Crystal Load Capacitance
[3]
Crystal Load Capacitance
[3]
Input Pin Capacitance
[3]
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Total Power Supply Current
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5V, V
DD
= 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of AV
DD
CMOS levels,% of AV
DD
V
IN
= AV
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
I
DDS
Total Power Supply Current in Shutdown active
Shutdown Mode
Min.
12
12
–
–
–
70%
–
–
–
–
–
–
–
100
50
5
Typ.
24
24
6
30
7
–
–
<1
<1
Max.
–
–
–
–
–
–
30%
10
10
10
–
–
20
Unit
mA
mA
pF
pF
pF
AV
DD
AV
DD
µA
µA
µA
mA
mA
µA
Switching Characteristics
Parameter
1/t
1
t
2
Name
Output Frequency
[3, 4]
Output Duty Cycle
[3, 5]
Description
Clock output limit, Commercial
Clock output limit, Industrial
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout < 100 MHz, divider >= 2, measured at V
DD
/2
Duty cycle for outputs, defined as t
2
÷
t
1
,
Fout > 100 MHz or divider = 1, measured at V
DD
/2
t
3
t
4
t
5
t
6
t
7
Rising Edge Slew Rate
[3]
Output clock rise time, 20% to 80% of V
DD
Falling Edge Slew
Rate
[3]
Output three-state
Timing
[3]
Clock Jitter
[3, 6]
Lock Time
[3]
Output clock fall time, 20% to 80% of V
DD
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
Peak-to-peak period jitter, CLK outputs measured
at V
DD
/2
PLL Lock Time from Power-up
Min.
–
–
45%
40%
0.75
0.75
–
–
–
Typ.
–
–
50%
50%
1.4
1.4
150
400
1.0
Max.
200
166
55%
60%
–
–
300
–
3
V/ns
V/ns
ns
ps
ms
Unit
MHz
MHz
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%–80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07013 Rev. *D
Page 5 of 8
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