CY22381
Pin Configuration
CY22381
8-pin SOIC
CLKC
GND
XTALIN
XTALOUT
1
2
3
4
8
7
6
5
FS/
SUSPEND
/OE/
SHUTDOWN
V
DD
CLKA
CLKB
Selector Guide
Part Number
CY22381FC
CY22381FI
Outputs
3
3
Input Frequency Range
Output Frequency Range
Specifics
Commercial Temperature
Industrial Temperature
8 MHz – 30 MHz (external crystal) Up to 200 MHz
1 MHz – 166 MHz (reference clock)
8 MHz – 30 MHz (external crystal) Up to 166 MHz
1 MHz – 150 MHz (reference clock)
Pin Summary
Name
CLKC
GND
XTALIN
XTALOUT
CLKB
CLKA
V
DD
FS/SUSPEND/
OE/SHUTDOWN
Pin Number
1
2
3
4
5
6
7
8
Description
Configurable clock output C
Ground
Reference crystal input or external reference clock input
Reference crystal feedback (float if XTALIN is driven by external reference clock)
Configurable clock output B
Configurable clock output A
Power supply
General Purpose Input. Can be Frequency Control, Suspend mode control, Output
Enable, or full-chip shutdown.
General-Purpose Input
The CY22381 features an output control pin (pin 8) that can
be programmed to control one of four features.
When programmed as a Frequency Select (FS), the input can
select between two arbitrarily programmed frequency settings.
The Frequency Select can change the following; the frequency
of PLL1, the output divider of CLKB, and the output divider of
CLKA. Any divider change as a result of switching the FS input
is guaranteed to be glitch free.
The general-purpose input can simultaneously control the
Suspend feature, turning off a set of PLLs and outputs deter-
mined during programming.
When programmed as an Output Enable (OE) the input forces
all outputs to be placed in a three-state condition when LOW.
When programmed as a Shutdown, the input forces a full chip
shutdown mode when LOW.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
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Operation
The CY22381 is an upgrade to the existing CY2081. The new
device has a wider frequency range, greater flexibility,
improved performance, and incorporates many features that
reduce PLL sensitivity to external system issues.
The device has three PLLs that allow each output to operate
at an independent frequencies. These three PLLs are
completely programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The frequency of PLL1 can optionally
be changed by using the external CMOS general purpose
input. See the following section on “General-Purpose Input” for
more detail.
PLL2 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an eight-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
Document #: 38-07012 Rev. *D
CYPRESS [ CYPRESS SEMICONDUCTOR ]
