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CG7C324-A20JCT 参数 Datasheet PDF下载

CG7C324-A20JCT图片预览
型号: CG7C324-A20JCT
PDF下载: 下载PDF文件 查看货源
内容描述: [OT PLD, 20ns, CMOS, PQCC28, PLASTIC, LCC-28]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 14 页 / 518 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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PLDC20RA10
Switching Characteristics
Over the Operating Range
Commercial
–15
Parameter
t
PD
t
EA
t
ER
t
PZX
t
PXZ
t
CO
t
SU
t
H
t
P
t
WH
t
WL
f
MAX
t
S
t
R
Description
Input or Feedback to
Non-Registered Output
Input to Output Enable
Input to Output
Disable
Pin 13 to Output
Enable
Pin 13 to Output
Disable
Clock to Output
Input or Feedback
Set-Up Time
Hold Time
Clock Period
(t
SU
+ t
CO)
Clock Width HIGH
Clock Width LOW
Maximum Frequency
(1/t
P
)
Input of Asynchronous
Set to Registered Output
Input of Asynchronous
Reset to Registered
Output
Asynchronous Reset
Width
Asynchronous S-Width
Asynchronous Set/
Reset Recovery Time
Preload Pulse Width
Preload Set-Up Time
Preload Hold Time
15
15
10
15
15
15
7
3
22
10
10
45.5
15
15
Min.
Max.
15
15
15
12
12
15
10
5
30
13
13
33.3
20
20
–20
Min.
Max.
20
20
20
15
15
20
10
3
30
12
12
33.3
20
20
–20
Min.
Max.
20
20
20
15
15
20
15
5
40
18
18
25.0
25
25
Military
–25
Min.
Max.
25
30
30
20
20
25
20
5
55
25
25
18.1
40
40
–35
Min.
Max.
35
35
35
25
25
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
t
ARW
t
ASW
t
AR
t
WP
t
SUP
t
HP
20
20
12
15
15
15
20
20
12
15
15
15
25
25
15
15
15
15
25
25
20
15
15
15
ns
ns
ns
ns
ns
ns
Notes:
7. Part (a) of AC Test Loads was used for all parameters except t
EA
, t
ER
, t
PZX
and t
PXZ
, which use part (b).
8. The parameters t
ER
and t
PXZ
are measured as the delay from the input disable logic threshold transition to V
OH
- 0.5 V for an enabled HIGH output or V
OL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
Document #: 38-03012 Rev. **
Page 7 of 14