欢迎访问ic37.com |
会员登录 免费注册
发布采购

CG7C324-A20JCT 参数 Datasheet PDF下载

CG7C324-A20JCT图片预览
型号: CG7C324-A20JCT
PDF下载: 下载PDF文件 查看货源
内容描述: [OT PLD, 20ns, CMOS, PQCC28, PLASTIC, LCC-28]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 14 页 / 518 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CG7C324-A20JCT的Datasheet PDF文件第1页浏览型号CG7C324-A20JCT的Datasheet PDF文件第3页浏览型号CG7C324-A20JCT的Datasheet PDF文件第4页浏览型号CG7C324-A20JCT的Datasheet PDF文件第5页浏览型号CG7C324-A20JCT的Datasheet PDF文件第6页浏览型号CG7C324-A20JCT的Datasheet PDF文件第7页浏览型号CG7C324-A20JCT的Datasheet PDF文件第8页浏览型号CG7C324-A20JCT的Datasheet PDF文件第9页  
PLDC20RA10  
Selection Guide  
tPD ns  
tSU ns  
tCO ns  
tCC ns  
Generic Part  
Number  
20RA10-15  
20RA10-20  
20RA10-25  
20RA10-35  
Coml  
Mil  
Coml  
7
Mil  
Coml  
15  
Mil  
Coml  
Mil  
15  
20  
80  
80  
20  
25  
35  
10  
10  
15  
20  
20  
20  
25  
35  
85  
85  
85  
Pin Configurations  
JEDEC PLCC/HLCC[1]  
Top View  
LCC  
Top View  
STD PLCC/HLCC  
Top View  
4
3 2 1 282726  
4
3
2
1
2827 26  
25  
4
3
2
1
2827 26  
25  
I
I
I
I
I
I
5
6
7
8
9
10  
11  
25  
24  
23  
NC  
I/O  
I/O  
I/O  
2
3
4
5
5
6
7
8
9
10  
11  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
2
3
4
5
6
7
5
6
7
8
9
10  
11  
I/O  
I/O  
I/O  
NC  
I/O  
I/O  
I/O  
I
I
I
2
2
3
4
2
3
4
I
I
24  
23  
22  
21  
20  
19  
3
4
24  
23  
22  
21  
20  
19  
3
4
5
PLDC20RA10 22  
PLDC20RA10  
NC  
21 I/O  
20 I/O  
19  
PLDC20RA10  
CG7C324  
6
7
NC  
I
I
I
I
5
6
5
5
6
7
6
NC  
I/O  
7
6
NC  
12131415161718  
NC  
I
121314 1516 1718  
7
121314 1516 1718  
RA102  
RA103  
RA104  
product terms and four uncommitted product terms of each  
programmable I/O macrocell that has been configured as an  
output.  
Macrocell Architecture  
Figure 1 illustrates the architecture of the 20RA10 macrocell.  
The cell dedicates three product terms for fully asynchronous  
control of the register set, reset, and clock functions, as well  
as, one term for control of the output enable function.  
An I/O cell is programmed as an input by tying the output en-  
able pin (pin 13) HIGH or by programming the output enable  
product term to provide a LOW, thereby disabling the output  
buffer, for all possible input combinations.  
The output enable product term output is ANDed with the input  
from pin 13 to allow either product term or hardwired external  
control of the output or a combination of control from both  
sources. If product-term-only control is selected, it is automat-  
ically chosen for all outputs since, for this case, the external  
output enable pin must be tied LOW. The active polarity of  
each output may be programmed independently for each out-  
put cell and is subsequently fixed. Figure 2 illustrates the out-  
put enable options available.  
When utilizing the I/O macrocell as an output, the input path  
functions as a feedback path allowing the output signal to be  
fed back as an input to the product term array. When the output  
cell is configured as a registered output, this feedback path  
may be used to feed back the current output state to the device  
inputs to provide current state control of the next output state  
as required for state machine implementation.  
Preload and Power-Up Reset  
When an I/O cell is configured as an output, combinatorial-only  
capability may be selected by forcing the set and reset product  
term outputs to be HIGH under all input conditions. This is  
achieved by programming all input term programming cells for  
these two product terms. Figure 3 illustrates the available out-  
put configuration options.  
Functional testability of programmed devices is enhanced by  
inclusion of register preload capability, which allows the state  
of each register to be set by loading each register from an  
external source prior to exercising the device. Testing of com-  
plex state machine designs is simplified by the ability to load  
an arbitrary state without cycling through long test vector se-  
quences to reach the desired state. Recovery from illegal  
states can be verified by loading illegal states and observing  
recovery. Preload of a particular register is accomplished by  
impressing the desired state on the register output pin and  
lowering the signal level on the preload control pin (pin1) to a  
logic LOW level. If the specified preload set-up, hold and pulse  
width minimums have been observed, the desired state is  
loaded into the register. To insure predictable system initializa-  
tion, all registers are preset to a logic LOW state upon pow-  
er-up, thereby setting the active LOW outputs to a logic HIGH.  
An additional four uncommitted product terms are provided in  
each output macrocell as resources for creation of user-de-  
fined logic functions.  
Programmable I/O  
Because any of the ten I/O pins may be selected as an input,  
the device input configuration programmed by the user may  
vary from a total of nine programmable plus ten dedicated in-  
puts (a total of nineteen inputs) and one output down to a  
ten-input, ten-output configuration with all ten programmable  
I/O cells configured as outputs. Each input pin available in a  
given configuration is available as an input to the four control  
Note:  
1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The  
principal difference is in the location of the no connect(NC) pins  
Document #: 38-03012 Rev. **  
Page 2 of 14  
 
 复制成功!