PRELIMINARY
TABLE OF CONTENTS
(continued)
CY82C693UB
DMA Register 37: DMAC2 Channel 7 Page Address Register (Read/Write) - Index=08AH ........................ 84
DMA Register 38: DMAC2 Channel 5 Page Address Register (Read/Write) - Index=08BH ........................ 85
DMA Register 39: DMAC1 Extended Mode Control (Write Only)
−
I/O Address=40BH .................................. 85
DMAC1 Extended Mode Control Register Format .......................................................................................... 85
DMA Register 40: DMAC1 Channel 2 High Page Address Register (Read/Write) - Index=481H ................ 85
DMA Register 41: DMAC1 Channel 3 High Page Address Register (Read/Write) - Index=482H ................ 85
DMA Register 42: DMAC1 Channel 1 High Page Address Register (Read/Write) - Index=483H ................ 85
DMA Register 43: DMAC1 Channel 0 High Page Address Register (Read/Write) - Index=487H ................ 85
DMA Register 44: DMAC2 Channel 6 High Page Address Register (Read/Write) - Index=489H ................ 86
DMA Register 45: DMAC2 Channel 7 High Page Address Register (Read/Write) - Index=48AH ............... 86
DMA Register 46: DMAC2 Channel 5 High Page Address Register (Read/Write) - Index=48BH ............... 86
DMA Register 47: DMAC2 Extended Mode Control (Write Only) - I/O Address=4D6H .................................. 86
DMAC2 Extended Mode Control Register Format .......................................................................................... 86
CY82C693UB IDE (Bus Mastering) DMA Controller Registers ............................................................. 87
SFF-8038i Registers ........................................................................................................................................ 87
Bus Master IDE Command Register Format (Offset+00H for Primary Channel;
Offset +08H for Secondary Channel) .............................................................................................................. 87
Bus Master IDE Status Register Format (Offset+02H for Primary Channel;
Offset +0AH for Secondary Channel) .............................................................................................................. 88
Bus Master IDE Descriptor Table Pointer Register Format
(Offset+04H-07H for Primary Channel; Offset +0CH-0FH for Secondary Channel) ....................................... 88
Bus Master IDE I/O Base Address Register (PCI Configuration Space, function 1, register address 20-23H) 88
hyperCache Specific (Not Required by SFF-8038i) Registers ........................................................................ 89
Bus Master IDE Channel 0 Configuration Register (I/O Address 22H with Data = 30 (Index Port);
I/O Address 23H is the Data Port) ................................................................................................................... 89
Bus Master IDE Channel 1 Configuration Register (I/O Address 22H with Data = 31 (Index Port);
I/O Address 23H is the Data Port) ................................................................................................................... 89
Bus Master IDE TimeOut Register (I/O Address 22H with Data = 32 (Index Port);
I/O Address 23H is the Data Port) - Write Only ............................................................................................... 89
Bus Master IDE Test Register (I/O Address 22H with Data = 33 (Index Port);
I/O Address 23H is the Data Port) ................................................................................................................... 89
CY82C693UB Interrupt Controller Registers ......................................................................................... 90
ICW1: INTC1 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=020H .............................. 91
ICW2: INTC1 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=021H .............................. 91
ICW3: INTC1 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=021H .............................. 92
ICW4: INTC1 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=021H .............................. 92
ICW1: INTC2 Interrupt Initialization Command Word 1 (Write Only) - I/O Address=0A0H ............................. 93
ICW2: INTC2 Interrupt Initialization Command Word 2 (Write Only) - I/O Address=0A1H ............................. 93
ICW3: INTC2 Interrupt Initialization Command Word 3 (Write Only) - I/O Address=0A1H ............................. 93
ICW4: INTC2 Interrupt Initialization Command Word 4 (Write Only) - I/O Address=0A1H ............................. 94
OCW1: INTC1 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=021H ........................... 94
OCW2: INTC1 Interrupt Operational Command Word 2 (Write Only) - I/O Address=020H ............................ 95
OCW3: INTC1 Interrupt Operational Command Word 3 (Write Only) - I/O Address=020H ............................ 95
OCW1: INTC2 Interrupt Operational Command Word 1 (Read/Write) - I/O Address=0A1H ........................... 96
OCW2: INTC2 Interrupt Operational Command Word 2 (Write Only) - I/O Address=0A0H ............................ 96
OCW3: INTC2 Interrupt Operational Command Word 3 (Write Only) - I/O Address=0A0H ............................ 97
CY82C693UB Timer/Counter Registers ................................................................................................ 98
Timer/Counter Register 0: Timer Control Word Register (Write Only) - Address=043H ................................. 98
Timer Control Word Register Format (Not Read-Back Command or Counter Latch Command) .................... 98
Timer Control Word Register Format (Read-Back Command) ........................................................................ 98
Timer Control Word Register Format (Counter Latch Command) ................................................................... 9 9
6
CYPRESS [ CYPRESS SEMICONDUCTOR ]
