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C9829BY 参数 Datasheet PDF下载

C9829BY图片预览
型号: C9829BY
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 20 页 / 349 K
品牌: CYPRESS [ CYPRESS ]
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+/+…when timing is critical  
C9829B  
Low EMI Clock Generator for Intel 133MHz/3DIMM Chipset Systems  
Approved Product  
Maximum Ratings  
This device contains circuitry to protect the inputs  
against damage due to high static voltages or electric  
field; however, precautions should be taken to avoid  
Maximum Input Voltage Relative to VSS: VSS - 0.3V  
Maximum Input Voltage Relative to VDD: VDD + 0.3V  
application of any voltage higher than the maximum  
rated voltages to this circuit. For proper operation, Vin  
and Vout should be constrained to the range:  
VSS<(Vin or Vout)<VDD  
Unused inputs must always be tied to an appropriate  
logic voltage level (either VSS or VDD).  
Storage Temperature:  
Operating Temperature:  
-65ºC to + 150ºC  
0ºC to +85ºC  
Maximum ESD protection  
Maximum Power Supply:  
2KV  
5.5V  
DC Parameters (All outputs loaded per table 5, page 12)  
Characteristic  
Symbol Min  
Typ  
Max  
Units  
Vdc  
Vdc  
Vdc  
Vdc  
µA  
Conditions  
Input Low Voltage  
VIL1  
VIH1  
VIL2  
VIH2  
IIL1  
-
-
-
-
-
1.0  
Note 1  
Input High Voltage  
2.0  
-
1.0  
-
Input Low Voltage  
-
Note 2  
Input High Voltage  
2.2  
Input Low Current (@VIL = VSS)  
Input High Current (@VIL =VDD)  
Input Low Current (@VIL = VSS)  
Input High Current (@VIL =VDD)  
Tri-State leakage Current  
Dynamic Supply Current  
Dynamic Supply Current  
Static Supply Current  
Input pin capacitance  
Output pin capacitance  
Pin inductance  
-66  
-5  
For internal Pull up resistors,  
Notes 1,3  
IIH1  
-5  
-
5
µA  
IIL2  
-5  
-
5
µA  
For internal Pull Down resistor  
Note 4  
IIH2  
5
-
66  
10  
360  
100  
10  
5
µA  
Ioz  
-
-
µA  
Idd3.3V  
Idd2.5V  
Isdd  
-
-
mA  
mA  
mA  
pF  
Sel(3:0) = 0001  
Sel(3:0) = 0001  
-
-
-
-
PD# =0, Sel(3:0) = x  
Cin  
-
-
Cout  
Lpin  
-
-
6
pF  
-
-
34  
7
nH  
Crystal pin capacitance  
Crystal DC Bias Voltage  
Crystal Startup time  
Cxtal  
VBIAS  
Txs  
32  
0.3Vdd  
-
38  
0.7Vdd  
40  
pF  
Measured from Pin to Ground. Note 5  
From Stable 3.3V power supply.  
Vdd/2  
-
V
µS  
VDD=VDDS = 3.3V 5%, VDDC = VDDI = 2.5 5%, TA = 0º to +70ºC  
±
±
Note1:  
Note2:  
Note3:  
Note4:  
Note5:  
Applicable to input signals: Sel(0:3), TS# / PD#  
Applicable to Sdata, and Sclk.  
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.  
Although internal pull-down resistor has a typical value of 50K, this value may vary between 30K and 70K.  
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF  
crystal specifications.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
Rev 1.3  
4/12/2000  
Page 13 of 20  
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