Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Byte 4: DRCG Control Register
(all bits are read and write functional)
Byte 5: Clock control register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
Bit
7
6
5
4
@Pup
Pin#
Description
7
0
-
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
Reserved
3V66_0 Output Enabled
1 = enabled, 0 = disabled
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3V66_5 Output Enable
1 = enabled, 0 = disabled
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
0
1
0
0
0
0
-
-
-
-
-
-
SS1 Spread Spectrum control bit
SS0 Spread Spectrum control bit
66IN to 66M delay Control MSB, See table
66IN to 66M delay Control LSB, See table
Reserved
48MDOT edge rate control. When set to 1,
the edge is slowed by 15%.
Reserved
6
5
0
1
-
33
4
3
2
1
0
1
1
1
1
1
35
24
23
22
21
3
2
1
0
0
0
-
-
USB edge rate control. When set to 1, the
edge is slowed by 15%
Byte 7: Watch Dog Time Stamp Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 6: Silicon Signature Register
(all bits are read only)
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
0
0
0
0
0
0
1
1
-
-
-
-
-
-
-
-
Vendor Code
011 = IMI
Byte 9: Dial-a-Frequency™ Control Register R
(all bits are read and write functional)
Note: When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
R6 MSB
R5
R4
R3
R2
R1
R0, LSB
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Byte 8: Dial-a-Frequency™ Control Register N
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
N7, MSB
N6
N5
N4
N3
N2
N3
N0, LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
66IN to 66M Delay Control Table
Byte5
Delay (ns)
Bit5
0
Bit4
0
4.29
0
1
4.43
1
1
0
1
3.95 (default)
3.95
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 5 of 25
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