C9820
Direct Rambus Clock Generator
Preliminary
System Clock Configuration (Cont.)
After comparing the phases of Pclk/M and SynClk/N, the C9820 Phase Detector drives a phase aligner that adjusts the
phase of the C9820 output clock, busclk. Since the other elements in the distributed loop have a fixed delay, adjusting
Busclk adjusts the phase of SynClk and thus the phase of SynClk/N.
In this manner, the distributed loop adjusts the phase of SynClk/N to match that of Pclk/M, eliminating the phase error at
the input of the C9820. When the clocks are aligned, data can be exchanged directly from the Pclk domain to the
SynClk domain.
The Gear Ratio Logic supports four clock ratios (1.0, 1.33, 2.0), where the ratio is defined as the ratio of Pclk/SynClk.
Since Busclk - 4*synClk, this ratio also is equal to 4*Pclk/busclk.
In addition, the device is able to receive input signals that are generated from different voltage power supplies. The
controller output voltage supply is connected to the pin VDDIPD of the C9820, and is used as the reference for the two-
phase detector input signal, PclkM and SynClkN. The output voltage supply is also used as the reference for the output
enable/disable signal, StopB.
The reference clock comes from the main clock source chip. The main clock source output voltage supply is connected
to the pin VDDlR of C9820, and is used as the reference for the Refclk input signal.
Table of frequencies and Gear Ratios
Gear Ratio Timing Diagram
Pclk
SynClk
Pclk/M =
SynClk/N
Figure: 4
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 4 of 17
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