+/+…when timing is critical
C9815C
Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems
Preliminary
Pin Description
PIN No.
Pin Name
PWR
I/O
Description
1
VDD
I/O This is a bi-directional pin (see app. note, p.5). At power up, it is an input pin
Sel2 for selecting the CPU/SDRAM frequencies (see table 1 p.1). When the
power reaches the rail, the state of Sel2 is latched, and this pin becomes REF, a
buffer output of the signal applied at Xin, typically 14.318MHz. This pin has an
Internal Pull-Down. Typical 50KΩ (range 20KΩ to 70KΩ)
SEL2/REF
3
4
VDD
VDD
I
On-chip reference oscillator input pin. Requires either an external parallel
resonant crystal (nominally 14.318 MHz) or externally generated reference signal
On-chip reference oscillator pin. Drives an external parallel resonant crystal.
When an externally generated reference signal is used at Xin, this pin remains
unconnected.
XIN
O
XOUT
12,13,15,
16,18,19, 20
7, 8, 9
25
26
VDD
O
3.3V PCI clock outputs. They are Synchronous to CPU clocks. See fig.3, page4.
PCI0_ICH
PCI(1..6)
3V66(0:2)
USB
DOT
SEL(0,1)
VDD
VDD
VDD
VDD
O
O
O
I
3.3V Fixed 66.6 MHz clock outputs. See fig.3 page 4.
3.3V Fixed 48 MHz clock outputs
3.3V Fixed 48 MHz clock outputs
3.3V LVTTL inputs for logic selection. This pin has an Internal Pull-Up. Typical
250KΩ (range 200KΩ to 500KΩ)
28, 29
30
VDD
I/O Serial data input pin. Conforms to the Philips I2C specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See I2C function
description, pp.6,7,8.
SDATA
31
32
VDD
VDD
I
I
Serial clock input pin. Conforms to the Philips I2C specification.
3.3V LVTTL compatible input. When held LOW, the device enters a power down
mode. See description page 3. This pin has an Internal Pull-Up. Typical 250KΩ
(range 200KΩ to 500KΩ)
SCLK
PD#
34
VDD
VDDS
VDDC
O
O
O
O
3.3V SDRAM feedback clock. See table1, p.1 for frequency selection. See fig.3,
page 4 for timing relationship.
3.3V SDRAM DIMM clocks. See table1, p.1 for frequency selection. See fig.3,
page 4 for timing relationship.
DCLK
36,37,39,40,
42,43,45, 46
49, 50, 52
SDRAM(7..0)
2.5V Host clock outputs. See table 1 p. 1 for frequency selection.
CPU(2)_ITP,C
PU(1,0)
IOAPIC(1,0)
VDD
54, 55
2,10, 11, 21,
27, 33
VDDI
-
2.5V IOAPIC clock outputs. See fig.3 p.4 for timing relationship.
3.3V Common Power Supply
22
23
51, 53
5, 6,14, 17,
24, 35, 41,
47, 48, 56
38, 44
-
-
-
-
Analog circuitry 3.3V Power Supply
Analog circuitry power supply Ground pins.
2.5V Power Supply’s
VDDA
VSSA
VDDC, VDDI
VSS
Common Ground pins.
-
3.3V power support for SDRAM clock output drivers.
VDDS
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Test Mode Function
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/5/2000
Page 2 of 18
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