+/+…when timing is critical
C9815B
Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems
Preliminary
Serial Control Registers
NOTE: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
and Byte 2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable)
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
-
-
-
Description
Reserved
Reserved
Reserved
Reserved
Spread spectrum mode
DOT
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
36
37
39
40
42
43
45
46
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
-
26
25
49
USB
CPU2_ITP
Byte 2: PCI Clock Register (1=Enable, 0=Disable)
Byte 3: Reserved Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
9
Description
3V66-2 (AGP)
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Reserved
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
0
20
19
18
16
15
13
-
0 = SDRAM runs at 100MHz
1= SDRAM runs at 133.3MHz
Byte 4: Reserved Register
Byte 5: SSCG Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Spread Mode (0=down, 1=center)
Selects spread bandwidth. Ref. Table 4
Selects spread bandwidth. Ref. Table 4
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.1
3/12/2000
Page 8 of 18
CYPRESS [ CYPRESS ]
