+/+…when timing is critical
C9810
Low EMI Clock Generator for Intel 810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
133 MHz Host
100 MHz Host
Symbol
Parameter
Units
Notes
Min
69.8413
1.0
Max
71.0
4.0
Min
69.8413
1.0
Max
71.0
4.0
TPeriod
Tr / Tf
REF period
nS
nS
pS
nS
nS
mS
%
5, 6, 8
6, 7
6, 8
13
REF rise and fall times
TCCJ
REF Cycle to Cycle Jitter
-
1000
10.0
10.0
3
-
1000
10.0
10.0
3
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
Duty Cycle for All outputs
1.0
1.0
1.0
1.0
13
12
Tduty
45
55
45
55
14
Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per table 5 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at
1.25V for 2.5V signals.
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Fig.8A and Fig.8B)
Note 8: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V signals. (see
Figs.8A & 8B)
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figs. 8A & 8B)
Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 13:Measured from when both SEL1 And SEL0 are low
Note 14: Device designed for Typical Duty Cycle of 50%.
Group Timing Relationships and Tolerances
CPU 100MHz
CPU 100MHz
CPU 133MHz
CPU 133MHz
CPU 66MHz
CPU 66MHz
Group
Conditions
Offset
Tolerance
Offset
Tolerance
Offset
Tolerance
Note 6
CPU to SDRAM
CPU to 3V66
2.5nS
7.5nS
500pS
500pS
5.0nS
5.0nS
500pS
500pS
0
0
500pS
500pS
CPU = 133.3MHz,
Notes 6, 7
CPU = 133.3MHz,
Notes 6, 7
SDRAM to 3V66
3V66 to PCI
0
500pS
500pS
0
500pS
500pS
0
500pS
500pS
CPU =
66.6/100/133.3MHz
Notes 6, 7
1.5~2.5nS
1.5~2.5nS
1.5~2.5nS
CPU =
66.6/100/133.3MHz
Notes 6, 7
PCI to APIC
USB to DOT
0
1.0nS
N/A
0
1.0nS
N/A
0
1.0nS
N/A
CPU =
66.6/100/133.3MHz
Notes 6, 7
Async
Async
Async
VDD=VDDS=3.3V ±5%, VDDC=VDDI=2.5±5%, TA=0 to 70ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Rev 0.4
8/31/1999
Page 12 of 15
http://www.imicorp.com
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