C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
-65ºC to + 150ºC
0ºC to +85ºC
Maximum ESD protection
Maximum Power Supply:
2000V
5.5V
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters (VDD = 3.3V ±5%, TA = 0º to +70ºC)
Characteristic
Symbol Min
Typ
Max
1.0
Units
Vdc
Vdc
µA
Conditions
Input Low Voltage
VIL2
VIH2
IIL
-
-
-
Note 2
Input High Voltage
2.2
-66
-
-5
5
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Output Low Voltage for Sreset
For internal Pull up resistors,
Notes 1,3
IIH
µA
IIL
-5
5
µA
For internal Pull down resistors,
Notes 1,3
IIH
66
0.4
24
µA
Vol
-
-
V
Iol = 24mA
Vol = 0.4V
Pull-Down current for Sreset
Iol
35
-
mA
Tri-State leakage Current
Dynamic Supply Current
Ioz
Idd3.3V
Idd3.3V
Cin
-
-
-
-
10
260
350
5
µA
mA
mA
pF
pF
nH
pF
V
S(3:0) = 1101, Note 4
S(3:0) = 0111, Note 4
-
-
Input pin capacitance
Output pin capacitance
Pin inductance
-
-
Cout
Lpin
-
-
6
-
-
7
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Cxtal
VBIAS
Txs
30
36
38
Measured from Pin to VSS. Note 5
From Stable 3.3V power supply.
0.3Vdd Vdd/2 0.7Vdd
-
-
40
µS
Note1:
Note2:
Note3:
Note4:
Note5:
Pull-down applicable to pin 25 (S3). Pull-up applicable to pins 2, 7, 8, 26, 48.
Applicable to Sdata, and Sclk.
Although internal pull-down/up resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per table 5 below.
Although the device will reliably interface with crystals of a 15pF – 20pF CL range, it is optimized to interface with a typical CL = 16pF
crystal specifications.
Clock Name
Max Load (in pF)
CPU, REF
PCI, SDRAM
24MHz, 48MHz
20
30
15
Table 5
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 12 of 17
CYPRESS [ CYPRESS ]
