APPROVED PRODUCT
®
C9630
PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications
Pin Description
PIN No.
2
Pin Name
S3/ REF0
PWR
VDD
I/O
I/O
Description
3.3V 14.318 MHz clock output. This Is a power on bi-directional pin.
During power up, this pin is an input “S3” for setting the CPU
frequency (see table1, page 1) (see app note, page 5). When the
power reaches the rail, this pin becomes a buffered output of the
signal applied at Xin (typically 14.318 MHz).
This pin is a buffered output of the signal applied at Xin (typically
14.318)
14.318MHz Crystal input
14.318MHz Crystal output
This is a power on bi-directional pin. During power up, this pin is an
input “S1” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI0 clock output.
This is a power on bi-directional pin. During power up, this pin is an
input “S2” for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI1 clock output.
3.3V PCI clock outputs.
This pin is programmable to 24MHz or 48 MHz clock output through
SMBus. It defaults to 24MHz at power up.
This is a power on bi-directional pin. During power up, this pin is an
input “S0” for setting the CPU frequency (see table1, page 1) (see
app note, page 5). When the power reaches the rail, this pin becomes
a 48MHz clock output. This clock conforms to the USB spec. of
+167ppm.
SMBus compatible SDATA input. Has an internal pull-up (>100KΩ)
SMBus compatible SCLK input. Has an internal pull-up (>100KΩ)
3.3V SDRAM clock outputs. See table1, p.1 for frequency selection.
48
4
5
7
REF1
XIN
XOUT
S1/ PCI0*
VDD
VDD
VDD
VDD
O
I
O
I/O
8
S2/ PCI1*
VDD
I/O
9,11,12,13,
14
25
26
PCI(2:6)
24/48MHz
S0 / 48MHz*
VDD
VDD
VDD
O
O
I/O
28
29
17,18,20,21,
28,29,31,32,
34,35,37,38,
40,41
43,45,46
1,6,15,19,
27, 30,36,42
47
3,10,16,22,
33,39,44
SDATA
SCLK
SDRAM(0:13)
VDD
VDD
VDD
I
I
O
CPU(0:2)
VDD
VDDC
VSS
VDDC
-
-
-
O
2.5V or 3.3V Host bus clock outputs. See table 1, page 1 for
frequency selection.
3.3V Common Power Supply
2.5V or 3.3V Power Supply’s for CPU (0:2) clock outputs.
Common Ground pin.
A bypass capacitor (0.1
µ
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
*Note: These pins have pulldown resistors, typical value 250
Ω.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 2 of 18
CYPRESS [ CYPRESS SEMICONDUCTOR ]
