+/+
Preliminary
Product Features
•
•
•
•
•
•
…when timing is critical
C9531
PCIX I/O System Clock Generator With EMI Control Features
•
•
•
•
•
•
Dedicated clock buffer power pins for reduced
noise, crosstalk and jitter
Buffer XIN Reference clock output
Input clock frequency 33.3 MHz
Output frequencies of 33.3, 66.6, 100 and 133.3
MHz selectable (PCIX requirements)
One output banks of 5 clocks.
2
I C clock control interface for individual clock
disabling, SSCG control and individual bank
frequency selection
Output clock duty cycle is 50% (± 5%)
<250 pS skew between output clocks within a
bank
Output jitter <175 pSec.
Spread Spectrum feature for reduced EMI
OE pins for entire output bank enable control and
testability
28 Pin SSOP and TSSOP package
Test Mode Logic Table
INPUT PINS
OE
HIGH
HIGH
HIGH
HIGH
LOW
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
OUTPUT PINS
CLK(0:4)
XIN
2 X XIN
3 X XIN
4 X XIN
Tri-State
REF
XIN
XIN
XIN
XIN
Tri-State
Note:
XIN is the frequency of the clock on the
device’s XIN pin.
Pin Configuration
Block Diagram
SSCG#
SSCG
Logic
/N
1
0
CLK0
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
SDATA
SCLK
VSS
VDDP
CLK0
CLK1
CLK2
VSS
VDDP
CLK3
CLK4
AVDD
VSS
SSCG#
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
C9531
XIN
XOUT
23
22
21
20
19
18
17
16
15
SDATA
SCLK
IA(0,1)
S(0,1)
I
2
C
Control
Logic
AVDD
OE
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/6/2000
Page 1 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
