+/+
Preliminary
Pin Description
Pin No.
3
4
1
14*
24, 23, 22,
19, 18
8
6*, 7*
Pin
Name
XIN
XOUT
REF
OE
…when timing is critical
C9531
PCIX I/O System Clock Generator With EMI Control Features
PWR
VDDA
VDDA
VDD
VDD
VDDP
VDD
VDD
I/O
I
O
O
I
O
O
I
Description
Crystal Buffer input pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can
Oscillator is used or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically 33.33
MHz
Output Enable for clock bank. Causes the CLK (0:4) output clocks to
be in a Tri-state condition when driven to a logic low level.
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x or 4x Xin clock).
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock.
Clock Bank selection bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
3.3V common power supply pin for all PCI clocks (CLK (0:4).
2
I2C address selection input pins. See I C Address table, pg. 4.
Enables Spread Spectrum clock modulation when at a logic low level,
see pg. 3.
2
Data for the internal I C circuitry, see pg. 4.
2
Clock for the internal I C circuitry, see pg. 4.
Power for internal analog circuitry. This supply should have a
separately decoupled current source from VDD.
Power supply for internal Core logic and the FOUT buffer
Ground pins for the device
CLK(0:4)
GOOD#
S(0,1)
20
10*, 11*,
12*
15*
28
27
13, 17
2, 25
5, 9, 16, 21,
26
VDDP
IA(0:2)
SSCG#
SDATA
SCLK
AVDD
VDD
VSS
VDD
VDD
VDD
VDD
-
-
-
PWR
I
I
I/O
I
I
PWR
PWR
Note:
Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no
external circuitry is connected to them.
A bypass capacitor (0.1
µF)
should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic will be cancelled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both
input and output functionality of the pin(s).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/6/2000
Page 2 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
