C9530
PCIX I/O System Clock Generator with EMI
Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33.3 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• Output grouped in two banks of five clocks each
• One REF XIN clock output
• SMBus clock control interface for individual clock
disabling and SSCG control and individual back
frequency selection
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter < 250 psec (175 psec with all outputs at the
same frequency)
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pins for entire output bank enable control and
testability
• 48-pin SSOP and TSSOP packages
Table 1. Test Mode Logic Table
[1]
Input Pins
OEA
OEB
HIGH
HIGH
HIGH
HIGH
LOW
SA1
SB1
LOW
LOW
HIGH
HIGH
X
SA0
SB0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLKA
CLKB
XIN
2 * XIN
3 * XIN
4 * XIN
Three-state
REF
XIN
XIN
XIN
XIN
Three-state
Block Diagram
Pin Configuration
REF
VDD
XIN
XOUT
VSS
SA0
SA1
VSS
CLKA0
CLKA1
VDDA
CLKA2
VSS
VDDA
CLKA3
CLKA4
VSS
AGOOD#
VSS
IA0
IA1
IA2
AVDD
OEA
1
2
3
4
5
6
7
8
9
10
48
47
46
45
44
43
42
41
40
39
SDATA
SCLK
VDD
VSS
VDD
SB0
SB1
VSS
CLKB0
CLKB1
VDDB
CLKB2
VSS
VDDB
CLKB3
CLKB4
VSS
BGOOD#
AVDD
AVDD
VSS
SSCG#
VSS
OEB
AGOOD#
SSCG#
SSCG
Logic
/N
1
0
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
OEA
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
OEB
BGOOD#
REF
XIN
XOUT
0
C9530
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDATA
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
/N
I
2
C
Control
Logic
1
Note:
1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device’s XIN pin. OEA and OEB will three-state
REF.
Cypress Semiconductor Corporation
Document #: 38-07033 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 31, 2005
CYPRESS [ CYPRESS SEMICONDUCTOR ]
