C5002
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG
Approved Product
Output Enable Control
The Output Enable Pin (pin 5) on this device serves two (2) purposes. The primary function is to force all clock outputs
to a tri-state electrical mode. This is done to support automated testing of fabricated PCB assemblies.
The second function of this pin is to bring the internal circuitry of the device to a lower power mode when the pin is driven
to a logic low level. In this mode, all unneeded circuitry (e.g., the PLL, counters and clock control logic) have their power
removed. Designers who use this functionality should pay close attention to the TOEL characteristic listed in the AC
Parameters section of this datasheet. This function is particularly useful in mobil designs where power savings is a
crucial design factor. Data stored in the SMBus registers is maintained during OE active periods.
Application Note for Selection on BI-DIRECTIONAL Pins
Vdd
Pins 10, 11, 14, 15, 18, 19, 22, 23, 26 and 27 are Power
up bi-directional pins and are used for selecting power
up output frequencies of this devices output clocks (see
Pin description, Page 2). During power-up of the device,
Rup
50K
C5002
these pins are in input mode, therefore, they are
considered input select pins internal to the IC, these
pins have a large value pull-up each (250KΩ), therefore,
a selection “1” is the default and will select a 66 MHz
output frequency. If the system uses a slow power
supply (over 5 ms settling time), then it is recommended
to use an external pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see FIG. 3A and Fig. 3B.
Rd
Load
Bidirectional
JP1
JUMPER
Fig. 3A
Rdn
5K
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in Fig.
3A. Please note the selection resistors (Rup and Rdn)
are placed before the Damping resistor (Rd) close to
the pin.
JP2
Vdd
3 Way Jumper
Fig. 3B represents a single resistor 10KΩ connected to
a 3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads 1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rsel
10K
C5002
Rd
Load
Bidirectional
Fig. 3B
If the system power supply is fast (less than 5 mSec
settling time), then FIG 3A only applies and Pull up Rup
resistor is not necessary.
The electrical length of the trace that connects the
selection resistor to the devices pin should be kept as
short as possible.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07014 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 5 of 16
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