BCM89359 Advance Data Sheet
WLAN/BT GPIO Signals and Strapping Options
WLAN/BT GPIO Signals and Strapping Options
The pins listed in Table 19 and Table 20 are sampled at power-on reset (POR) to determine the various
operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR.
After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.
Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default
mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ
resistor or less.
Note: Refer to the reference board schematics for more information.
Table 19: BT GPIO Functions and Strapping Options
Default
Pin Name
Function Description
1: BT Serial Flash is present.
0: BT Serial Flash is absent (default).
BT_GPIO2
0
Note: Not valid on wireless charging platform.
Strapping Options
Table 20: GPIO Strap Pins
Default Pull
During Strapping
Pin Name
All Packages
GPIO_7
0
0
1
1
1
JTAG_ENABLE
RSRC_INIT_0
RSRC_INIT_1
VTRIM_EN
GPIO_14
GPIO_15
GPIO_16
GPIO_17
SDIO_PADVDDIO: 0 ≥ 3.3V, 1 ≥ 1.8V; when SDIO is enabled
(strap from GPIO_18 is 0).
SPROM_ABSENT: 0 ≥ SPROM present, 1 ≥ SPROM absent;
when SDIO is disabled (strap from GPIO_18 is 1).
GPIO_18
GPIO_19
1
1
SDIO_DISABLE: 0 ≥ SDIO enabled, 1 ≥ SDIO disabled; either
PCIe or SDIO or both have to be present.
PCIE_ENABLE: 0 ≥ PCIe disabled, 1 ≥ PCIe enabled; either
PCIe or SDIO or both have to be present.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 83
BROADCOM CONFIDENTIAL
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