BCM89359 Advance Data Sheet
Signal Descriptions
Table 18: BCM89359 WLBGA Signal Descriptions (Cont.)
Signal Name Type Description
Ball
RF Switch Control Lines
E6
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
RF_SW_CTRL_5
RF_SW_CTRL_6
RF_SW_CTRL_7
RF_SW_CTRL_8
RF_SW_CTRL_9
RF_SW_CTRL_10
RF_SW_CTRL_11
RF_SW_CTRL_12
RF_SW_CTRL_13
RF_SW_CTRL_14
RF_SW_CTRL_15
RF_SW_CTRL_16
RF_SW_CTRL_17
RF_SW_CTRL_18
RF_SW_CTRL_19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Programmable RF switch control lines. The control
lines are programmable via the driver and NVRAM
file.
F6
F5
G5
H5
F4
G4
H4
H3
H2
N10
N11
P12
M10
M11
N12
K9
L9
L11
L12
WLAN PCI Express Interface
E12
PCIE_CLKREQ_L
OD PCIe clock request signal which indicates when
the REFCLK to the PCIe interface can be gated.
1 = the clock can be gated.
0 = the clock is required.
E11
PCIE_PERST_L
I (PU) PCIe System Reset. This input is the PCIe reset as
defined in the PCIe base specification version 1.1.
C12
D12
A12
B12
A11
A10
E10
PCIE_RDN0
PCIE_RDP0
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_TDN0
I
I
Receiver differential pair (×1 lane).
I
PCIE Differential Clock inputs (negative and
positive). 100 MHz differential.
I
O
O
Transmitter differential pair (×1 lane).
PCIE_TDP0
PCI_PME_L
OD PCI power management event output. Used to
request a change in the device or system power
state. The assertion and deassertion of this signal
is asynchronous to the PCIe reference clock. This
signal has an open-drain output structure, as per
the PCI Bus Local Bus Specification, revision 2.3.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 77
BROADCOM CONFIDENTIAL
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