BCM89359 Advance Data Sheet
Debug UART Interface
Figure 22: Legacy 3-Wire LTE Coexistence Interface
GCI_GPIO_2
GCI_GPIO_1
WCN_PRIORITY
WLAN
GCI
MWS_RX, LTE_PRIORITY
LTE_FRAME_SYNC
GCI_GPIO_0
BT
LTE/IC
Note: OR’ing to generate WCN_PRIORITY FOR ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
Debug UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins. Refer to
Table 22: “GPIO Alternative Signal Functions,” on page 85. Provided primarily for debugging during
development, this UART enables the BCM89359 to operate as RS-232 data termination equipment (DTE) for
exchanging and managing data with other serial devices. It is compatible with the industry standard 16550
UART, and provides a FIFO size of 64 × 8 in each direction.
FAST UART Interface
A high-speed 4-wire CTS/RTS UART interface can be enabled by software as an alternate function on GPIO
pins. Refer to Table 22: “GPIO Alternative Signal Functions,” on page 85. Provided primarily for control word
exchange, this UART enables the chip to operate as RS-232 data termination equipment (DTE) for exchanging
and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and
provides a FIFO size of 64 × 8 in each direction.
JTAG Interface
The BCM89359 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist
customers by using proprietary debug and characterization test tools during board bringup. Therefore, it is highly
recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
Refer to Table 22: “GPIO Alternative Signal Functions,” on page 85 for JTAG pin assignments.
Broadcom®
September 9, 2014 • 89359-DS100-R
Page 57
BROADCOM CONFIDENTIAL
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