BCM88335 Data Sheet
WLAN GPIO Signals and Strapping Options
WLAN GPIO Signals and Strapping Options
The pins listed in Table 16 are sampled at power-on reset (POR) to determine the various operating modes.
Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR,
each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping
option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change
the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kꢀ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 16: WLAN GPIO Functions and Strapping Options
WLBGA
Pin #
Default
Function
Pin Name
Description
SDIO_SELa
GPIO_7
D4
1
GPIO_8
H1
0
1
SDIO_PADVDDIO
CPU-LESSa
SPI_SELa
SDIO_CLK
B11
SDIO_DATA_2
D10
1
a. See Table 17 and Table 18.
Table 17: SDIO/gSPI I/O Voltage Selection
SDIO_SEL
SPI_SEL
SDIO_PADVDDIO
Mode
1
1
0
0
0
X
X
1
1
0
0
1
0
1
X
1.8V I/O
3.3V I/O
1.8V I/O
3.3V I/O
3.3V I/O
Table 18: Host Interface Selection (WLBGA Package)
SDIO_SEL
SPI_SEL
CPULESS
Mode
1
0
0
0
X
1
0
0
X
X
0
1
SDIO Mode (3.3V or 1.8V I/O)
gSPI Mode (3.3V or 1.8V I/O)
Unsupported
Unsupported
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 82
BROADCOM CONFIDENTIAL
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