BCM88335 Data Sheet
WLAN Power Management
WLAN Power Management
All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries
were chosen to reduce leakage current and supply voltages. Additionally, the BCM88335 integrated RAM is a
high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage
current only. Additionally, the BCM88335 includes an advanced WLAN power management unit (PMU)
sequencer. The PMU sequencer provides significant power savings by putting the BCM88335 into various
power management states appropriate to the current environment and activities that are being performed. The
power management unit enables and disables internal regulators, switches, and other blocks based on a
computation of the required resources and a table that describes the relationship between resources and the
time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-
running counters (running at the 32.768 kHz LPO clock frequency) in the PMU sequencer are used to turn on
and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated
altogether) for the current mode. Slower clock speeds are used wherever possible.
The BCM88335 WLAN power states are described as follows:
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•
Active mode— All WLAN blocks in the BCM88335 are powered up and fully functional with active carrier
sensing and frame transmission and receiving. All required regulators are enabled and put in the most
efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of
the BCM88335 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are
shut down to reduce active power consumption to the minimum. The 32.768 kHz LPO clock is available
only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip
and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.
•
•
Deep-sleep mode—Most of the chip, including both analog and digital domains, and most of the regulators
are powered off. Logic states in the digital core are saved and preserved into a retention memory in the
always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU
timers, an external interrupt, or a host resume through the SDIO bus, logic states in the digital core are
restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization.
Power-down mode—The BCM88335 is effectively powered off by shutting down all internal regulators. The
chip is brought out of this mode by external logic reenabling the internal regulators.
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 23
BROADCOM CONFIDENTIAL
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