BCM88335 Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: BCM88335 Block Diagram ............................................................................................................... 17
Figure 3: Typical Power Topology for the BCM88335 ..................................................................................... 22
Figure 4: Recommended Oscillator Configuration ........................................................................................... 26
Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 27
Figure 6: Startup Signaling Sequence ............................................................................................................. 38
Figure 7: CVSD Decoder Output Waveform Without PLC............................................................................... 40
Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 40
Figure 9: Functional Multiplex Data Diagram................................................................................................... 44
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 45
Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 46
Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 47
Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 48
Figure 14: UART Timing .................................................................................................................................. 49
2
Figure 15: I S Transmitter Timing.................................................................................................................... 52
2
Figure 16: I S Receiver Timing........................................................................................................................ 52
Figure 17: Broadcom GCI or BT-SIG Mode LTE Coexistence Interface for the BCM88335 ........................... 54
Figure 18: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 57
Figure 19: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 57
Figure 20: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 58
Figure 21: gSPI Write Protocol ........................................................................................................................ 59
Figure 22: gSPI Read Protocol ........................................................................................................................ 59
Figure 23: gSPI Command Structure............................................................................................................... 60
Figure 24: gSPI Signal Timing Without Status (32-bit Big Endian).................................................................. 61
Figure 25: gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) ..................................... 62
Figure 26: WLAN Boot-Up Sequence.............................................................................................................. 65
Figure 27: WLAN MAC Architecture ................................................................................................................ 66
Figure 28: WLAN PHY Block Diagram............................................................................................................. 71
Figure 29: Radio Functional Block Diagram .................................................................................................... 73
Figure 30: 145-Ball WLBGA (Top View) .......................................................................................................... 74
Figure 31: ........................................................................................................................................................ 74
Figure 32: Port Locations for Bluetooth Testing............................................................................................... 93
Figure 33: Port Locations Showing Optional ePA and eLNA (Applies to 2.4 GHz and 5 GHz) ..................... 100
Figure 34: SDIO Bus Timing (Default Mode) ................................................................................................. 121
Figure 35: SDIO Bus Timing (High-Speed Mode).......................................................................................... 122
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 10
BROADCOM CONFIDENTIAL
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