BCM43907 Preliminary Data Sheet
USB PHY Electrical Characteristics and Timing
USB 2.0 Timing Diagrams
Figure 36 shows the important timing parameters associated with a post-reset transition to high-speed (HS)
operation.
Figure 36: USB 2.0 Bus Reset to High-Speed Mode Operation
40 to 60 μs
< 100 μs
100 to 500 μs
DP
Idle
Idle
HS Data
High-
Speed
Chirp
Device
K-Chirp
DM
HS Data
3 to 3.125 ms
> 1.0 ms
100 to
875 μs
< 7 ms
> 10 ms
Start of Host
End of Host
(Hub) Chirp
End of
Reset
Device Goes
(Hub) Chirp
Start of
Reset
into Full-
Device Tests for
Single-Ended Zero
(SE0) State
Speed Mode
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 119
BROADCOM CONFIDENTIAL
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