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BCM43903KUBG 参数 Datasheet PDF下载

BCM43903KUBG图片预览
型号: BCM43903KUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [WICED™ IEEE 802.11 a/b/g/n SoC with anEmbedded Applications Processor]
分类和应用:
文件页数/大小: 65 页 / 1225 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
CYW43903  
During each clock cycle, the PMU sequencer performs the following actions:  
Computes the required resource set based on requests and the resource dependency table.  
Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource  
and inverts the ResourceState bit.  
Compares the request with the current resource status and determines which resources must be enabled or disabled.  
Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up depen-  
dents.  
Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.  
2.5 Power-Off Shutdown  
The CYW43903 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system  
devices remain operational. When the CYW43903 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO  
remains powered. This allows the CYW43903 to be effectively off while keeping the I/O pins powered so that they do not draw extra  
current from devices connected to the I/O.  
During a low-power shutdown state, provided VDDIO remains applied to the CYW43903, all outputs are tristated and most inputs  
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths  
or create loading on any digital signals in the system, and enables the CYW43903 to be fully integrated in an embedded device while  
taking full advantage of the lowest power-saving modes.  
When the CYW43903 is powered on from this state, it is the same as a normal power-up and does not retain any information about  
its state from before it was powered down.  
2.6 Power-Up/Power-Down/Reset Circuits  
The CYW43903 has two signals (see Table 3) that enable or disable circuits and the internal regulator blocks, allowing the host to  
control power consumption. For timing diagrams of these signals and the required power-up sequences, see Power-Up Sequence  
and Timing.  
Table 3. Power-Up/Power-Down/Reset Control Signals  
Signal  
REG_ON  
Description  
This signal is used by the PMU to power up the CYW43903. It controls the internal CYW43903 regulators.  
When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device  
is in reset and the regulators are disabled. This pin has an internal 200 kpull-down resistor that is enabled  
by default. It can be disabled through programming.  
HIB_REG_ON_IN  
This signal is used by the hibernation block to decide whether or not to power down the internal CYW43903  
regulators. If HIB_REG_ON_IN is low, the regulators will be disabled. For a signal at HIB_REG_ON_IN to  
function as intended, HIB_REG_ON_OUT must be connected to REG_ON.  
Document Number: 002-14826 Rev. *G  
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