BCM4356 Advance Data Sheet
List of Figures
Figure 36: RF Port Location for Bluetooth Testing......................................................................................... 130
Figure 37: Port Locations (Applies to 2.4 GHz and 5 GHz) ........................................................................... 142
Figure 38: SDIO Bus Timing (Default Mode) ................................................................................................. 169
Figure 39: SDIO Bus Timing (High-Speed Mode).......................................................................................... 171
Figure 40: SDIO Clock Timing (SDR Modes) ................................................................................................ 172
Figure 41: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 173
Figure 42: SDIO Bus Output Timing (SDR Modes up to 100 MHz)............................................................... 174
Figure 43: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 175
Figure 44: ∆tOP Consideration for Variable Data Window (SDR 104 Mode) ................................................ 176
Figure 45: SDIO Clock Timing (DDR50 Mode).............................................................................................. 177
Figure 46: SDIO Data Timing (DDR50 Mode) ............................................................................................... 178
Figure 47: WLAN = ON, Bluetooth = ON ....................................................................................................... 183
Figure 48: WLAN = OFF, Bluetooth = OFF.................................................................................................... 183
Figure 49: WLAN = ON, Bluetooth = OFF ..................................................................................................... 184
Figure 50: WLAN = OFF, Bluetooth = ON ..................................................................................................... 184
Figure 51: WLAN Boot-Up Sequence............................................................................................................ 185
Figure 52: WLAN/PCIe Power-Up Timing...................................................................................................... 186
Figure 53: 192-Ball WLBGA Package Mechanical Information ..................................................................... 189
Figure 54: WLBGA Keep-Out Areas for PCB Layout (Top View, Balls Facing Down) .................................. 190
Figure 55: 395-Bump WLCSP Package ........................................................................................................ 191
Figure 56: WLCSP Keep-Out Areas for PCB Layout (Top View, Balls Facing Down)................................... 192
Broadcom®
May 8, 2015 • 4356-DS103-R
Page 11
BROADCOM CONFIDENTIAL
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