BCM4354 Data Sheet
PCM Interface
Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty
cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to
24 MHz. This mode of operation is initiated with an HCI command from the host.
PCM Interface Timing
Short Frame Sync, Master Mode
Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM _SYNC
PCM _OUT
8
HIGH IMPEDANCE
5
7
6
PCM_IN
Table 7: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No. Characteristics Minimum Typical Maximum Unit
1
2
3
4
5
6
7
8
PCM bit clock frequency
–
–
–
–
–
–
–
–
–
12
–
MHz
ns
PCM bit clock LOW
PCM bit clock HIGH
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
41
41
0
–
ns
25
25
–
ns
0
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
0
25
ns
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 47
BROADCOM CONFIDENTIAL
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