BCM4354 Data Sheet
HSIC Interface Specifications
HSIC Interface Specifications
Table 59: HSIC Interface Parameters
Parameter
Symbol Minimum
Typical
Maximum
1.3
Unit
Comments
HSIC signaling voltage
I/O voltage input low
I/O Voltage input high
I/O voltage output low
I/O voltage output high
I/O pad drive strength
VDD
VIL
1.1
1.2
–
V
V
V
V
V
ꢀ
–
–
–
–
–
–0.3
0.35 × VDD
VDD + 0.3
0.25 × VDD
–
VIH
VOL
VOH
OD
0.65 × VDD
–
–
–
0.75 × VDD
40
–
–
60
Controlled output
impedance driver
I/O weak keepers
IL
20
100
3
–
70
–
mA
kꢀ
pF
ꢀ
–
–
–
–
I/O input impedance
ZI
CL
TI
–
Total capacitive loada
–
14
55
Characteristic trace
impedance
45
50
Circuit board trace length TL
–
–
–
–
10
15
cm
ps
–
–
Circuit board trace
propagation skewb
TS
STROBE frequencyc
Slew rate (rise and fall)
STROBE and DATAC
FSTROBE 239.988
Tslew
240
240.012
1.2
MHz
V/ns
± 500 ppm
0.60 × VDD 1.0
Averaged from
30% ~ 70% points
Receiver data setup time Ts
(with respect to STROBE)c
300
300
–
–
–
–
ps
ps
Measured at the
50% point
Receiver data hold time
Tb
Measured at the
50% point
(with respect to STROBE)c
a. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50ꢀ PCB trace with
a length of 10 cm.
b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be
matched between STROBE and DATA to ensure that the signal timing is within specification limits at the
receiver.
c. Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the
Table 59.
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 176
BROADCOM CONFIDENTIAL
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